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LH28F160S5-L/S5H-L
LH28F160S5-L/S5H-L
DESCRIPTION
The LH28F160S5-L/S5H-L flash memories with Smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications, having high programming performance is achieved through highly-optimized page buffer operations. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S5-L/S5H-L offer three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F160S5-L/S5H-L are conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs.
16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)
* High performance read access time LH28F160S5-L70 - 70 ns (5.00.25 V)/80 ns (5.00.5 V) LH28F160S5H-L70 - 70 ns (5.00.25 V)/90 ns (5.00.5 V) LH28F160S5-L10/S5H-L10 - 100 ns (5.00.5 V) * Enhanced automated suspend options - Write suspend to read - Block erase suspend to write - Block erase suspend to read * Enhanced data protection features - Absolute protection with VPP = GND - Flexible block locking - Erase/write lockout during power transitions * SRAM-compatible write interface * User-configurable x8 or x16 operation * High-density symmetrically-blocked architecture - Thirty-two 64 k-byte erasable blocks * Enhanced cycling capability - 100 000 block erase cycles - 3.2 million block erase cycles/chip * Low power management - Deep power-down mode - Automatic power saving mode decreases ICC in static mode * Automated write and erase - Command user interface - Status register * ETOXTM V nonvolatile flash technology * Packages - 56-pin TSOP Type I (TSOP056-P-1420) Normal bend/Reverse bend - 56-pin SSOP (SSOP056-P-0600)5 [LH28F160S5-L] - 64-ball CSP (FBGA064-P-0811) - 64-pin SDIP (SDIP064-P-0750)5
ETOX is a trademark of Intel Corporation. 5 Under development
FEATURES
* Smart 5 technology - 5 V VCC - 5 V VPP * High speed write performance - Two 32-byte page buffers - 2 s/byte write transfer rate * Common Flash Interface (CFI) - Universal & upgradable interface * Scalable Command Set (SCS)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH28F160S5-L/S5H-L
COMPARISON TABLE
VERSIONS LH28F160S5-L70/L10 LH28F160S5H-L70/L10 OPERATING TEMPERATURE 0 to +70C - 40 to +85C ACCESS TIME DC CHARACTERISTICS at 5.00.5 V VCC deep power-down current (MAX.) 80 ns/100 ns 90 ns/100 ns 15 A 20 A PACKAGE 56-pin TSOP (I), 56-pin SSOP5, 64-ball CSP, 64-pin SDIP5 56-pin TSOP (I), 64-ball CSP, 64-pin SDIP5
5 Under development
PIN CONNECTIONS
56-PIN TSOP (Type I)
NC CE1# NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0# VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
5 Under development
56-PIN SSOP5 [LH28F160S5-L]
WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC CE0# A12 A13 A14 A15 NC CE1# NC A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 STS OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND
(TSOP056-P-1420)
(SSOP056-P-0600)
NOTE :
Reverse bend available on request.
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LH28F160S5-L/S5H-L
PIN CONNECTIONS (contd.)
64-BALL CSP
1 A NC B A17 C A15 D A12 E F G RP# A9 A7 2 A20 A18 VCC
CE0#
5 Under development
64-PIN SDIP5
3 NC A19 A14 A13 A11 A10 A5 A3 4 NC
CE1#
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
5 WP# WE# DQ6 NC NC DQ9 NC NC
6 OE# DQ15 DQ5 DQ12 DQ3 DQ10 DQ0
BYTE#
7 STS DQ7 GND VCC GND VCC DQ8 A0
8 NC DQ14 DQ13 DQ4 DQ11 DQ2 DQ1 NC
A16 NC NC GND A2 A1
VPP A8 A6 A4
H NC
(FBGA064-P-0811)
VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 NC NC NC NC NC NC NC BYTE# A0 DQ0 DQ8 DQ1 DQ9 VCC DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CE0# A12 A13 A14 A15 VCC A16 A17 A18 A19 A20 NC CE1# NC NC NC NC WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND
(SDIP064-P-0750)
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LH28F160S5-L/S5H-L
BLOCK DIAGRAM
DQ0-DQ15
OUTPUT BUFFER
INPUT BUFFER
QUERY ROM OUTPUT MULTIPLEXER I/O LOGIC IDENTIFIER REGISTER DATA REGISTER PAGE BUFFER COMMAND USER INTERFACE
VCC BYTE# CE# WE# OE# RP# WP#
STATUS REGISTER
MULTIPLEXER DATA COMPARATOR
A0-A20
INPUT BUFFER
Y DECODER
Y GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH
STS VPP
ADDRESS LATCH
X DECODER
32 64 k-BYTE BLOCKS
VCC GND
ADDRESS COUNTER
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LH28F160S5-L/S5H-L
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. A0 : Byte Select Address. Not used in x16 mode (can be floated). A1-A4 : Column Address. Selects 1 of 16-bit lines. A5-A15 : Row Address. Selects 1 of 2 048-word lines. A16-A20 : Block Address. DATA INPUT/OUTPUTS : DQ0-DQ7 : Inputs data and commands during CUI write cycles; outputs data during memory array, status register, query, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ8-DQ15 : Inputs data during CUI write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register, query and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode (BYTE# = VIL). Data is internally latched during a write cycle. CHIP ENABLE : Activates the device's control logic, input buffers decoders, and sense amplifiers. Either CE0# or CE1# VIH deselects the device and reduces power consumption to standby levels. Both CE0# and CE1# must be VIL to select the devices. RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits write operations which provide data protection during power transitions. Exit from deep power-down sets the device to read array mode. OUTPUT ENABLE : Gates the device's outputs during a read cycle. WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). STS High Z indicates that the WSM is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. For alternate configurations of the STATUS pin, see the Configuration command (Table 3 and Section 4.14). WRITE PROTECT : Master control for block locking. When VIL, locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. BYTE ENABLE : BYTE# VIL places device in x8 mode. All data are then input or output on DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode, and turns off the A0 input buffer. BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCKBIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or configuring block lock-bits. With VPP VPPLK, memory contents cannot be altered. Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation. Do not float any power pins. With VCC VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. GROUND : Do not float any ground pins. NO CONNECT : Lead is not internal connected; recommend to be floated.
A0-A20
INPUT
DQ0-DQ15
INPUT/ OUTPUT
CE0#, CE1#
INPUT
RP# OE# WE#
INPUT INPUT INPUT
STS
OPEN DRAIN OUTPUT
WP# BYTE#
INPUT INPUT
VPP
SUPPLY
VCC GND NC
SUPPLY SUPPLY
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LH28F160S5-L/S5H-L
1 INTRODUCTION
This datasheet contains LH28F160S5-L/S5H-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F160S5-L/ S5H-L flash memories documentation also includes ordering information which is referenced in Section 7. word/byte write and block lock-bit configuration operations. A block erase operation erases one of the device's 64 k-byte blocks typically within 0.34 second (5 V VCC, 5 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (3.2 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. A word/byte write is performed in byte increments typically within 9.24 s (5 V VCC, 5 V VPP). A multi word/byte write has high speed write performance of 2 s/byte (5 V VCC, 5 V VPP). (Multi) word/byte write suspend mode enables the system to read data from, or write data to any other flash memory array location. Individual block locking uses a combination of bits and WP#, thirty-two block lock-bits, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. Block lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) set and cleared block lock-bits. The status register indicates when the WSM's block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. The STS output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using STS minimizes both CPU overhead and system power consumption. STS pin can be configured to different states using the Configuration command. The STS pin defaults to RY/BY# operation. When low, STS indicates that the WSM is performing a
1.1
Product Overview
The LH28F160S5-L/S5H-L are high-performance 16 M-bit Smart 5 flash memories organized as 2 MB x 8/1 MB x 16. The 2 MB of data is arranged in thirty-two 64 k-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Fig.1. Smart 5 technology provides a choice of VCC and VPP combination, as shown in Table 1, to meet system performance and power expectations. VPP at 5 V eliminates the need for a separate 12 V converter, while VPP = 5 V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP VPPLK.
Table 1 VCC and VPP Voltage Combination Offered by Smart 5 Technology VCC VOLTAGE 5V VPP VOLTAGE 5V
Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi)
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LH28F160S5-L/S5H-L
block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. STS High Z indicates that the WSM is ready for a new command, block erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down mode. The other 3 alternate configurations are all pulse mode for use as a system interrupt. The access time is 70 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70C (LH28F160S5-L)/- 40 to +85C (LH28F160S5H-L). At 4.5 to 5.5 V VCC, the access time is 80 ns/100 ns (LH28F160S5-L70/S5-L10) or 90 ns/100 ns (LH28F160S5H-L70/S5H-L10). The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC. When either CE0# or CE1#, and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.
1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block 64 k-Byte Block
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig. 1 Memory Map
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LH28F160S5-L/S5H-L
2 PRINCIPLES OF OPERATION
The LH28F160S5-L/S5H-L flash memories include an on-chip WSM to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. It allows for : 100% TTLlevel control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2.1 and Table 2.2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register, query structure and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. All functions associated with altering memory contents--block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes--are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. Interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to VPPH1. The device accommodates either design practice and encourages optimization of the processormemory interface. When VPP VPPLK, memory contents cannot be altered. The CUI, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations.
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LH28F160S5-L/S5H-L
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
3.4
Deep Power-Down
RP# at VIL initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, RP#-low will abort the operation. STS remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1
Read
Information can be read from any block, identifier codes, query structure, or status register independent of the VPP voltage. RP# must be at VIH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component : CE# (CE0#, CE1#), OE#, WE#, RP# and WP#. CE0#, CE1# and OE# must be driven active to obtain data at the outputs. CE0# and CE1# are the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. WE# and RP# must be at VIH. Fig. 15 and Fig. 16, illustrate a read cycle.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.
3.3
Standby
Either CE0# or CE1# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, the device continues functioning, and consuming active power until the operation completes.
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LH28F160S5-L/S5H-L
3.5
Read Identifier Codes Operation
The read identifier codes operation outputs the manufacture code, device code, block status codes for each block (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition.
component. Query structures are always presented on the lowest-order data output (DQ0-DQ7) only.
3.7
Write
Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCC = VCC1/2 and VPP = VPPH1, the CUI additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/Byte Write command requires the command and address of the location to be written. Set Block Lock-Bit command requires the command and block address within the device (Block Lock) to be locked. The Clear Block LockBits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 17 and Fig. 18 illustrate WE# and CE#-controlled write operations.
1FFFFF
Reserved for Future Implementation
1F0006 1F0005 1F0004 1F0003 1F0000 1EFFFF 020000 01FFFF
Block 31 Status Code Reserved for Future Implementation Block 31 (Blocks 2 through 30)
Reserved for Future Implementation
010006 010005 010004 010003 010000 00FFFF
Block 1 Status Code Reserved for Future Implementation
Block 1
Reserved for Future Implementation
000006 000005 000004 000003 000002 000001 000000
4 COMMAND DEFINITIONS
When the VPP voltage VPPLK, read operations from the status register, identifier codes, query, or blocks are enabled. Placing VPPH1 on VPP enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.
Block 0 Status Code Device Code Manufacture Code Block 0
Fig. 2 Device Identifier Code Memory Map
3.6
Query Operation
The query operation outputs the query structure. Query database is stored in the 48-byte ROM. Query structure allows system software to gain critical information for controlling the flash
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LH28F160S5-L/S5H-L
Table 2.1 Bus Operations (BYTE# = VIH) MODE Read Output Disable Standby Deep Power-Down Read Identifier Codes Query Write NOTE 1, 2, 3, 9 3 3 4 9 9 3, 7, 8, 9 RP# VIH VIH VIH VIL VIH VIH VIH CE0# VIL VIL VIH VIH VIL X VIL VIL VIL CE1# VIL VIL VIH VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL ADDRESS X X X X See Fig. 2 See Table 6 through 10 X VPP X X X X X X X DQ0-15 DOUT High Z High Z High Z STS X X X High Z
(NOTE 5) High Z (NOTE 6) High Z DIN X
Table 2.2 Bus Operations (BYTE# = VIL) MODE Read Output Disable Standby Deep Power-Down Read Identifier Codes Query Write NOTE 1, 2, 3, 9 3 3 4 9 9 3, 7, 8, 9 RP# VIH VIH VIH VIL VIH VIH VIH CE0# VIL VIL VIH VIH VIL X VIL VIL VIL CE1# VIL VIL VIH VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH
4. 5. 6. 7.
WE# VIH VIH X X VIH VIH VIL
ADDRESS X X X X See Fig. 2 See Table 6 through 10 X
VPP X X X X X X X
DQ0-7 DOUT High Z High Z High Z
STS X X X High Z
(NOTE 5) High Z (NOTE 6) High Z DIN X
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP VPPLK, memory contents can be read, but not altered. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1 voltages. STS is VOL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power-down mode. RP# at GND0.2 V ensures the lowest deep powerdown current. See Section 4.2 for read identifier code data. See Section 4.5 for query data. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when VPP = VPPH1 and VCC = VCC1/2. Refer to Table 3 for valid DIN during a write operation. Don't use the timing both OE# and WE# are VIL.
2.
3.
8. 9.
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LH28F160S5-L/S5H-L
Table 3 Command Definitions (NOTE 10) FIRST BUS CYCLE SECOND BUS CYCLE BUS CYCLES COMMAND NOTE REQ'D. Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Read Array/Reset 1 Write X FFH Read Identifier Codes 2 4 Write X 90H Read IA ID Query 2 Write X 98H Read QA QD Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase Setup/Confirm 2 5 Write BA 20H Write BA D0H Full Chip Erase Setup/Confirm 2 Write X 30H Write X D0H Word/Byte Write Setup/Write 2 5, 6 Write WA 40H Write WA WD Alternate Word/Byte Write 2 5, 6 Write WA 10H Write WA WD Setup/Write Multi Word/Byte Write 4 9 Write WA E8H Write WA N-1 Setup/Confirm Block Erase and (Multi) 1 5 Write X B0H Word/Byte Write Suspend Confirm and Block Erase and 1 5 Write X D0H (Multi) Word/Byte Write Resume Block Lock-Bit Set 2 7 Write BA 60H Write BA 01H Setup/Confirm Block Lock-Bit Reset 2 8 Write X 60H Write X D0H Setup/Confirm STS Configuration Level-Mode for Erase 2 Write X B8H Write X 00H and Write (RY/BY# Mode) STS Configuration 2 Write X B8H Write X 01H Pulse-Mode for Erase STS Configuration 2 Write X B8H Write X 02H Pulse-Mode for Write STS Configuration Pulse-Mode 2 Write X B8H Write X 03H for Erase and Write
NOTES :
1. 2. Bus operations are defined in Table 2.1 and Table 2.2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. QA = Query offset address. BA = Address within the block being erased or locked. WA = Address of memory location to be written. SRD = Data read from status register. See Table 13.1 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. QD = Data read from query database. Following the Read Identifier Codes command, read operations access manufacture, device and block status codes. See Section 4.2 for read identifier code data. 5. If the block is locked, WP# must be at VIH to enable block erase or (multi) word/byte write operations. Attempts to issue a block erase or (multi) word/byte write to a locked block while RP# is VIH. 6. Either 40H or 10H is recognized by the WSM as the byte write setup. 7. A block lock-bit can be set while WP# is VIH. 8. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. 9. Following the Third Bus Cycle, inputs the write address and write data of "N" times. Finally, input the confirm command "D0H". 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
3.
4.
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LH28F160S5-L/S5H-L
4.1
Read Array Command
NOTE :
1. X selects the specific block status code to be read. See Fig. 2 for the device identifier code memory map.
Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend and (Multi) Word/Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# must be VIH.
4.3
Read Status Register Command
4.2
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and block erase status (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# must be VIH. Following the Read Identifier Codes command, the following information can be read :
Table 4 Identifier Codes CODE ADDRESS 00000H Manufacture Code 00001H 00002H Device Code 00003H X0004H (NOTE 1) Block Status Code X0005H (NOTE 1) * Block is Unlocked * Block is Locked * Last erase operation completed successfully * Last erase operation did not completed successfully * Reserved for Future Use
The status register may be read to determine when a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully (see Table 13.1). It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE# (Either CE0# or CE1#), whichever occurs. OE# or CE# (Either CE0# or CE1#) must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# must be VIH. The extended status register may be read to determine multi byte write availability (see Table 13.2). The extended status register may be read at any time by writing the Multi Byte Write command. After writing this command, all subsequent read operations output data from the extended status register, until another valid command is written. The contents of the extended status register are latched on the falling edge of OE# or CE# (Either CE0# or CE1#), whichever occurs last in the read cycle. Multi Byte Write command must be re-issued to update the extended status register latch.
DATA B0 D0
4.4
DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 DQ2-7
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 13.1). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in
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LH28F160S5-L/S5H-L
sequence) may be performed. The status register may be polled to determine if an error occurs during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# must be VIH. This command is not functional during block erase, full chip erase, (multi) word/byte write, block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes. to any information or reserved for future use are set to "0". This command functions independently of the VPP voltage. RP# must be VIH.
Table 5 Example of Query Structure Output MODE OFFSET ADDRESS A5, A4, A3, A2, A1, A0 1, 0, 0, 0, 0, 0 (20H) x8 mode 1, 0, 0, 0, 0, 1 (21H) 1, 0, 0, 0, 1, 0 (22H) 1, 0, 0, 0, 1, 1 (23H) A5, A4, A3, A2, A1 x16 mode 1, 0, 0, 0, 0 (10H) 1, 0, 0, 0, 1 (11H) High Z High Z High Z High Z 00H 00H "Q" "Q" "R" "R" "Q" "R" OUTPUT DQ15-8 DQ7-0
4.5
Query Command
Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 6 through Table 10 retrieve the critical information to write, erase and otherwise control the flash component. A0 of query offset address is ignored when x8 mode (BYTE# = VIL). Query data are always presented on the low-byte data output (DQ0-DQ7). In x16 mode, high-byte (DQ8-DQ15) outputs 00H. The bytes not assigned
4.5.1 BLOCK STATUS REGISTER
This field provides lock configuration and erase status for the specified block. These informations are only available when device is ready (SR.7 = 1). If block erase or full chip erase operation is finished irregularly, block erase status bit will be set to "1". If bit 1 is "1", this block is invalid.
Table 6 Query Block Status Register OFFSET (Word Address) (BA+2)H LENGTH 01H Block Status Register bit0 Block Lock Configuration 0 = Block is unlocked 1 = Block is locked Block Erase Status 0 = Last erase operation completed successfully 1 = Last erase operation not completed successfully bit2-7 Reserved for future use DESCRIPTION
bit1
NOTE :
BA = The beginning of a Block Address.
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LH28F160S5-L/S5H-L 4.5.2 CFI QUERY IDENTIFICATION STRING
The identification string provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported.
Table 7 CFI Query Identification String OFFSET (Word Address) 10H, 11H, 12H 13H, 14H 15H, 16H 17H, 18H 19H, 1AH LENGTH 03H 02H 02H 02H 02H DESCRIPTION Query Unique ASCII string "QRY" 51H, 52H, 59H Primary Vendor Command Set and Control Interface ID Code 01H, 00H (SCS ID Code) Address for Primary Algorithm Extended Query Table 31H, 00H (SCS Extended Query Table Offset) Alternate Vendor Command Set and Control Interface ID Code 0000H (0000H means that no alternate exists) Address for Alternate Algorithm Extended Query Table 0000H (0000H means that no alternate exists)
4.5.3 SYSTEM INTERFACE INFORMATION
The following device information can be useful in optimizing system interface software.
Table 8 System Information String OFFSET (Word Address) 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H LENGTH 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H DESCRIPTION VCC Logic Supply Minimum Write/Erase voltage 27H (2.7 V) VCC Logic Supply Maximum Write/Erase voltage 55H (5.5 V) VPP Programming Supply Minimum Write/Erase voltage 27H (2.7 V) VPP Programming Supply Maximum Write/Erase voltage 55H (5.5 V) Typical Time-Out per Single Byte/Word Write 03H (23 = 8 s) Typical Time-Out for Maximum Size Buffer Write (32 Bytes) 06H (26 = 64 s) Typical Time-Out per Individual Block Erase 0AH (0AH = 10, 210 = 1 024 ms) Typical Time-Out for Full Chip Erase 0FH (0FH = 15, 215 = 32 768 ms) Maximum Time-Out per Single Byte/Word Write, 2N times of typical. 04H (24 = 16, 8 s x 16 = 128 s) Maximum Time-Out per Maximum Size Buffer Write, 2N times of typical. 04H (24 = 16, 64 s x 16 = 1 024 s) Maximum Time-Out per Individual Block Erase, 2N times of typical. 04H (24 = 16, 1 024 ms x 16 = 16 384 ms) Maximum Time-Out for Full Chip Erase, 2N times of typical. 04H (24 = 16, 32 768 ms x 16 = 524 288 ms)
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LH28F160S5-L/S5H-L 4.5.4 DEVICE GEOMETRY DEFINITION
This field provides critical details of the flash device geometry.
Table 9 Device Geometry Definition OFFSET (Word Address) 27H 28H, 29H 2AH, 2BH 2CH 2DH, 2EH 2FH, 30H LENGTH 01H 02H 02H 01H 02H 02H Device Size 15H (15H = 21, 221 = 2 097 152 = 2 M Bytes) Flash Device Interface Description 02H, 00H (x8/x16 supports x8 and x16 via BYTE#) Maximum Number of Bytes in Multi Word/Byte Write 05H, 00H (25 = 32 Bytes ) Number of Erase Block Regions within Device 01H (symmetrically blocked) The Number of Erase Blocks 1FH, 00H (1FH = 31 31 + 1 = 32 Blocks) The Number of "256 Bytes" cluster in a Erase Block 00H, 01H (0100H = 256 256 Bytes x 256 = 64k Bytes in a Erase Block) DESCRIPTION
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LH28F160S5-L/S5H-L 4.5.5 SCS OEM SPECIFIC EXTENDED QUERY TABLE
Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional vendor-specific query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s).
Table 10 SCS OEM Specific Extended Query Table OFFSET (Word Address) 31H, 32H, 33H 34H 35H 36H, 37H, 38H, 39H LENGTH 03H 01H 01H 04H PRI 50H, 52H, 49H 31H (1) Major Version Number , ASCII 30H (0) Minor Version Number, ASCII 0FH, 00H, 00H, 00H Optional Command Support bit0 = 1 : Chip Erase Supported bit1 = 1 : Suspend Erase Supported bit2 = 1 : Suspend Write Supported bit3 = 1 : Lock/Unlock Supported bit4 = 0 : Queued Erase Not Supported 3AH 01H bit5-31 = 0 : Reserved for future use 01H Supported Functions after Suspend bit0 = 1 : Write Supported after Erase Suspend 3BH, 3CH 02H bit1-7 = 0 : Reserved for future use 03H, 00H Block Status Register Mask bit0 = 1 : Block Status Register Lock Bit [BSR.0] active bit1 = 1 : Block Status Register Valid Bit [BSR.1] active 3DH 3EH 3FH 01H 01H reserved bit2-15 = 0 : Reserved for future use VCC Logic Supply Optimum Write/Erase voltage (highest performance) 50H (5.0 V) VPP Programming Supply Optimum Write/Erase voltage (highest performance) 50H (5.0 V) Reserved for future versions of the SCS specification DESCRIPTION
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LH28F160S5-L/S5H-L
4.6
Block Erase Command
4.7
Full Chip Erase Command
Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the STS pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC = VCC1/2 and VPP = VPPH1. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or if set, that WP# = VIH. If block erase is attempted when the corresponding block lock-bit is set and WP# = VIL, SR.1 and SR.5 will be set to "1".
This command followed by a confirm command (D0H) erases all of the unlocked blocks. A full chip erase setup is first written, followed by a full chip erase confirm. After a confirm command is written, device erases the all unlocked blocks from block 0 to block 31 block by block. This command sequence requires appropriate sequencing. Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect full chip erase completion by analyzing the output data of the STS pin or status register bit SR.7. When the full chip erase is complete, status register bit SR.5 should be checked. If erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. If error is detected on a block during full chip erase operation, WSM stops erasing. Reading the block valid status by issuing Read ID Codes command or Query command informs which blocks failed to its erase. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VCC = VCC1/2 and VPP = VPPH1. In the absence of this high voltage, block contents are protected against erasure. If full chip erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". When WP# = VIH, all blocks are erased independent of block lock-bits status. When WP# = VIL, only unlocked blocks are erased. In this case, SR.1 and SR.4 will not be set to "1". Full chip erase can not be suspended.
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LH28F160S5-L/S5H-L
4.8
Word/Byte Write Command
Word/byte write is executed by a two-cycle command sequence. Word/Byte Write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Fig. 5). The CPU can detect the completion of the word/byte write event by analyzing the STS pin or status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when VCC VCC1/2 and VPP = VPPH1. In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while VPP VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP# = VIH. If word/byte write is attempted when the corresponding block lock-bit is set and WP# = VIL, SR.1 and SR.4 will be set to "1". Word/byte write operations with VIL < WP# < VIH produce spurious results and should not be attempted.
=
4.9
Multi Word/Byte Write Command
Multi word/byte write is executed by at least fourcycle or up to 35-cycle command sequence. Up to 32 bytes in x8 mode (16 words in x16 mode) can be loaded into the buffer and written to the flash array. First, multi word/byte write setup (E8H) is written with the write address. At this point, the
device automatically outputs extended status register data (XSR) when read (see Fig. 6 and Fig. 7). If extended status register bit XSR.7 is 0, no Multi Word/Byte Write command is available and multi word/byte write setup which just has been written is ignored. To retry, continue monitoring XSR.7 by writing multi word/byte write setup with write address until XSR.7 transitions to "1". When XSR.7 transitions to "1", the device is ready for loading the data to the buffer. A word/byte count (N)-1 is written with write address. After writing a word/byte count (N)-1, the device automatically turns back to output status register data. The word/byte count (N)-1 must be less than or equal to 1FH in x8 mode (0FH in x16 mode). On the next write, device start address is written with buffer data. Subsequent writes provide additional device address and data, depending on the count. All subsequent address must lie within the start address plus the count. After the final buffer data is written, write confirm (D0H) must be written. This initiates WSM to begin copying the buffer data to the flash array. An invalid Multi Word/Byte Write command sequence will result in both status register bits SR.4 and SR.5 being set to "1". For additional multi word/byte write, write another multi word/byte write setup and check XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F160S5-L/S5H-L have two buffers. If an error occurs while writing, the device will stop writing and flush next Multi Word/Byte Write command loaded in Multi Word/Byte Write command. Status register bit SR.4 will be set to "1". No Multi Word/Byte Write command is available if either SR.4 or SR.5 is set to "1". SR.4 and SR.5 should be cleared before issuing Multi Word/Byte Write command. If a Multi Word/Byte Write command is attempted past an erase block boundary, the device will write the data to flash array up to an erase block boundary and then stop writing. Status register bits SR.4 and SR.5 will be set to "1".
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LH28F160S5-L/S5H-L
Reliable multi byte writes can only occur when VCC VCC1/2 and VPP = VPPH1. In the absence of this high voltage, memory contents are protected against multi word/byte writes. If multi word/byte write is attempted while VPP VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful multi word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP# = VIH. If multi byte write is attempted when the corresponding block lock-bit is set and WP# = VIL, SR.1 and SR.4 will be set to "1". suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 8). VPP must remain at VPPH1 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH. Block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed.
=
4.10 Block Erase Suspend Command
The Block Erase Suspend command allows block erase interruption to read or (multi) word/byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). STS will also transition to High Z. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A (Multi) Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the (Multi) Word/Byte Write Suspend command (see Section 4.11), a (multi) word/byte write operation can also be suspended. During a (multi) word/byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the STS (if set to RY/BY#) output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is
4.11 (Multi) Word/Byte Write Suspend Command
The (Multi) Word/Byte Write Suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. Once the (multi) word/byte write process starts, writing the (Multi) Word/Byte Write Suspend command requests that the WSM suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the (Multi) Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to "1"). STS will also transition to High Z. Specification tWHRH1 defines the (multi) word/byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while (multi) word/byte write is suspended are Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR.2
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LH28F160S5-L/S5H-L
and SR.7 will automatically clear and STS will return to VOL. After the (Multi) Word/Byte Write command is written, the device automatically outputs status register data when read (see Fig. 9). VPP must remain at VPPH1 (the same VPP level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. WP# must also remain at VIH or VIL. the absence of this high voltage, block lock-bit contents are protected against alteration. A successful set block lock-bit operation requires WP# = VIH. If it is attempted with WP# = VIL, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations with WP# < VIH produce spurious results and should not be attempted.
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. With WP# = VIH, individual block lock-bits can be set using the Set Block Lock-Bit command. See Table 12 for a summary of hardware and software write protection options. Set block lock-bit is executed by a two-cycle command sequence. The set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set block lockbit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Fig. 10). The CPU can detect the completion of the set block lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set block lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VCC = VCC1/2 and VPP = VPPH1. In
4.13 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With WP# = VIH, block lock-bits can be cleared using only the Clear Block Lock-Bits command. See Table 12 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lockbits setup is first written. After the command is written, the device automatically outputs status register data when read (see Fig. 11). The CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block LockBits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VCC = VCC1/2 and VPP = VPPH1. If a clear block lockbits operation is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are
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LH28F160S5-L/S5H-L
protected against alteration. A successful clear block lock-bits operation requires WP# = VIH. If it is attempted with WP# = VIL, SR.1 and SR.5 will be set to "1" and the operation will fail. Clear block lock-bits operation with VIH < RP# produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transition out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. configurations are all pulse mode for use as a system interrupt. The STS Configuration command functions independently of the VPP voltage and RP# must be VIH.
Table 11 STS Configuration Coding Description CONFIGURATION BITS EFFECTS Set STS pin to default level mode 00H (RY/BY#). RY/BY# in the default level-mode of operation will indicate WSM status condition. Set STS pin to pulsed output signal for specific erase operation. In this 01H mode, STS provides low pulse at the completion of Block Erase, Full Chip Erase and Clear Block Lock-Bits operations. Set STS pin to pulsed output signal 02H for a specific write operation. In this mode, STS provides low pulse at the completion of (Multi) Byte Write and Set Block Lock-Bit operation. Set STS pin to pulsed output signal for specific write and erase operation. STS provides low pulse at the completion of Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration operations.
4.14 STS Configuration Command
The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or RP# is set to VIL. Upon initial device power-up and after exit from deep power-down mode, the STS pin defaults to RY/BY# operation where STS low indicates that the WSM is busy. STS High Z indicates that the WSM is ready for a new operation. To reconfigure the STS pin to other modes, the STS Configuration is issued followed by the appropriate configuration code. The three alternate
03H
Table 12 Write Protection Alternatives BLOCK OPERATION WP# EFFECT LOCK-BIT Block Erase or 0 VIL or VIH Block Erase and (Multi) Word/Byte Write Enabled (Multi) Word/Byte VIL Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled 1 Write VIH Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled 0, 1 VIL All unlocked blocks are erased, locked blocks are not erased Full Chip Erase X VIH All blocks are erased Set Block Lock-Bit Disabled VIL Set Block Lock-Bit X VIH Set Block Lock-Bit Enabled VIL Clear Block Lock-Bits Disabled Clear Block Lock-Bits X VIH Clear Block Lock-Bits Enabled
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LH28F160S5-L/S5H-L
Table 13.1 Status Register Definition
WSMS 7
BESS 6
ECBLBS 5
WSBLBS 4
VPPS 3 NOTES :
WSS 2
DPS 1
R 0
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed
Check STS or SR.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS STS configuration attempt, an improper command sequence was entered. (ECBLBS)
1 = Error in Erase or Clear Block Lock-Bits 0 = Successful Erase or Clear Block Lock-Bits SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS (WSBLBS) 1 = Error in Write or Set Block Lock-Bit 0 = Successful Write or Set Block Lock-Bit SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = WRITE SUSPEND STATUS (WSS) 1 = Write Suspended 0 = Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Block Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPP VPPH1. SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates block lock-bit, and WP# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set and/or WP# is not VIH. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register.
Table 13.2 Extended Status Register Definition
SMS 7
R 6
R 5
R 4
R 3 NOTES :
R 2
R 1
R 0
XSR.7 = STATE MACHINE STATUS (SMS) 1 = Multi Word/Byte Write available 0 = Multi Word/Byte Write not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
After issue a Multi Word/Byte Write command : XSR.7 indicates that a next Multi Word/Byte Write command is available. XSR.6-0 are reserved for future use and should be masked out when polling the extended status register.
- 23 -
LH28F160S5-L/S5H-L
Start
BUS COMMAND OPERATION Write Read Read Status Register
COMMENTS Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 70H Read Status Register
Standby
SR.7 = 1
0
Write Erase Setup Erase Confirm
Data = 20H Addr = Within Block to be Erased Data = D0H Addr = Within Block to be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 20H, Block Address Write D0H, Block Address
Write Read
Standby
Read Status Register No SR.7 = 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4, 5 = 0 SR.5 = 0 Block Erase Successful 1 Block Erase Error Command Sequence Error 1 Device Protect Error VPP Range Error 0 Suspend Block Erase Loop Yes
Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last block erase operation to place device in read array mode.
Suspend Block Erase
BUS COMMAND OPERATION Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL, Block Lock-Bit is Set Only required for systems implementing block lock-bit configuration Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
Standby
Standby Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
Fig. 3 Automated Block Erase Flowchart
- 24 -
LH28F160S5-L/S5H-L
Start
BUS COMMAND OPERATION Write Read Read Status Register
COMMENTS Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 70H
Read Status Register
Standby
SR.7 = 1 Write 30H
0
Write Write Read
Full Chip Erase Setup
Data = 30H Addr = X
Data = D0H Full Chip Erase Confirm Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write D0H
Standby
Read Status Register
Full status check can be done after each full chip erase. Write FFH after the last full chip erase operation to place device in read array mode.
SR.7 = 1
0
Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS COMMAND OPERATION Standby COMMENTS Check SR.3 1 = VPP Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Full Chip Erase Error
1 SR.3 = 0
Standby
VPP Range Error
Standby
SR.4, 5 = 0
1
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
1 SR.5 = 0 Full Chip Erase Successful Full Chip Erase Error
Fig. 4 Automated Full Chip Erase Flowchart
- 25 -
LH28F160S5-L/S5H-L
Start
BUS COMMAND OPERATION Write Read Status Register
COMMENTS Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 70H
Read
Read Status Register
Standby
SR.7 = 1
0
Write Write Read
Setup Word/ Byte Write Word/Byte Write
Data = 40H or 10H Addr = Location to be Written Data = Data to be Written Addr = Location to be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register No SR.7 = 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 0 Suspend Word/Byte Write Loop Yes
Standby
Repeat for subsequent word/byte writes. SR full status check can be done after each word/byte write or after a sequence of word/byte writes. Write FFH after the last word/byte write operation to place device in read array mode.
Suspend Word/Byte Write
BUS COMMAND OPERATION Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL, Block Lock-Bit is Set Only required for systems implementing block lock-bit configuration Check SR.4 1 = Data Write Error
1 SR.3 = 0 1 Device Protect Error VPP Range Error
Standby
SR.1 = 0
Standby
1 SR.4 = 0 Word/Byte Write Successful
Word/Byte Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
Fig. 5 Automated Word/Byte Write Flowchart
- 26 -
LH28F160S5-L/S5H-L
Start Write E8H, Start Address Read Status Register No XSR.7 = 1 Write Word or Byte Count (N)_1, Start Address Write Buffer Data, Start Address X=0 0 Write Buffer Time-Out Yes
BUS COMMAND OPERATION Write Read
COMMENTS
Setup Multi Data = E8H Word/Byte Write Addr = Start Address Extended Status Register Data Check XSR.7 1 = Multi Word/Byte Write Ready 0 = Multi Word/Byte Write Busy Data = Word or Byte Count (N)_1 Addr = Start Address Data = Buffer Data Addr = Start Address Data = Buffer Data Addr = Device Address Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Standby Write (NOTE 1) Write (NOTE 2, 3) Write (NOTE 4, 5) Write Read
Abort Buffer Write Command? No
Yes
Standby
Write Another Block Address Multi Word/Byte Write Abort
Write Buffer Data, Device Address Yes
X=N No X=X+1
NOTES : 1. Byte or word count values on DQ0-7 are loaded into the count register. 2. Write buffer contents will be programmed at the start address. 3. Align the start address on a write buffer boundary for maximum programming performance. 4. The device aborts the Multi Word/Byte Write command if the current address is outside of the original block address. 5. The status register indicates an "improper command sequence" if the Multi Word/Byte Write command is aborted. Follow this with a Clear Status Register command. SR full status check can be done after each multi word/byte write or after a sequence of multi word/byte writes.
Write D0H
Write FFH after the last multi word/byte write operation to place device in read array mode.
Another Yes Buffer Write ? No Read Status Register No Suspend Multi Word/Byte Write Loop Suspend Yes Multi Word/Byte Write
SR.7 = 1
0
Full Status Check if Desired Multi Word/Byte Write Complete
Fig. 6 Automated Multi Word/Byte Write Flowchart
- 27 -
LH28F160S5-L/S5H-L
FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register
BUS COMMAND OPERATION Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL, Block Lock-Bit is Set Only required for systems implementing block lock-bit configuration Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Data Write Error
SR.3 = 0
1
VPP Range Error
Standby
SR.1 = 0
1
Device Protect Error
Standby Standby
SR.4, 5 = 0
1
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
SR.4 = 0
1
Multi Word/Byte Write Error
Multi Word/Byte Write Successful
Fig. 7 Full Status Check Procedure for Automated Multi Word/Byte Write
- 28 -
LH28F160S5-L/S5H-L
Start
BUS OPERATION Write
COMMAND Erase Suspend
COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed
Write B0H
Read
Read Status Register
Standby
SR.7 = 1
0
Standby
Write
Erase Resume
Data = D0H Addr = X
SR.6 = 1 Read
0
Block Erase Completed
Read or Write? No Done? Yes Write D0H
(Multi) Word/Byte Write (Multi) Word/Byte Write Loop
Read Array Data
Write FFH
Block Erase Resumed
Read Array Data
Fig. 8 Block Erase Suspend/Resume Flowchart
- 29 -
LH28F160S5-L/S5H-L
Start
BUS OPERATION Write
COMMAND (Multi) Word/ Byte Write Suspend
COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = (Multi) Word/Byte Write Suspended 0 = (Multi) Word/Byte Write Completed
Write B0H
Read
Read Status Register
Standby
SR.7 = 1
0
Standby
SR.2 = 1 Write FFH
0
(Multi) Word/Byte Write Completed
Write Read
Read Array
Data = FFH Addr = X Read array locations other than that being written.
Write
(Multi) Word/ Byte Write Resume
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
(Multi) Word/Byte Write Resumed
Read Array Data
Fig. 9 (Multi) Word/Byte Write Suspend/Resume Flowchart
- 30 -
LH28F160S5-L/S5H-L
Start
BUS OPERATION Write
COMMAND Set Block Lock-Bit Setup Set Block Lock-Bit Confirm
COMMENTS Data = 60H Addr = Block Address Data = 01H Addr = Block Address Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H, Block Address
Write 01H, Block Address
Write
Read
Read Status Register
Standby
0 SR.7 = 1 Full Status Check if Desired
Repeat for subsequent block lock-bit set operations. Full status check can be done after each block lock-bit set operation or after a sequence of block lock-bit set operations. Write FFH after the last block lock-bit set operation to place device in read array mode.
Set Block Lock-Bit Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS COMMAND OPERATION Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Block Lock-Bit Error
SR.3 = 0
1
VPP Range Error
Standby
SR.1 = 0
1
Standby
Device Protect Error
Standby
SR.4, 5 = 0
1
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple block lock-bits are set before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
SR.4 = 0
1
Set Block Lock-Bit Error
Set Block Lock-Bit Successful
Fig. 10 Set Block Lock-Bit Flowchart
- 31 -
LH28F160S5-L/S5H-L
Start
BUS OPERATION Write
COMMAND Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
COMMENTS Data = 60H Addr = X
Write 60H
Write D0H
Write
Data = D0H Addr = X
Read
Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Read Status Register
Standby
0 SR.7 = 1 Full Status Check if Desired
Write FFH after the last clear block lock-bits operation to place device in read array mode.
Clear Block Lock-Bits Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS COMMAND OPERATION Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error
SR.3 = 0
1
VPP Range Error
Standby
SR.1 = 0
1
Standby
Device Protect Error
Standby
SR.4, 5 = 0
1
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the status register before attempting retry or other error recovery.
SR.5 = 0
1
Clear Block Lock-Bits Error
Clear Block Lock-Bits Successful
Fig. 11 Clear Block Lock-Bits Flowchart
- 32 -
LH28F160S5-L/S5H-L
5 DESIGN CONSIDERATIONS 5.3 5.1 Three-Line Output Control
The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Threeline control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.4 5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Polling
VPP Trace on Printed Circuit Boards
STS is an open drain output that should be connected to VCC by a pullup resistor to provide a hardware method of detecting block erase, full chip erase, (multi) word/byte write and block lock-bit configuration completion. In default mode, it transitions low after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. For alternate STS pin configurations, see the Configuration command (Table 3 and Section 4.14). STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes.
Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
5.5
VCC, VPP, RP# Transitions
Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1 range, VCC falls outside of a valid VCC1/2 range, or RP# = VIL. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, STS (if set to
- 33 -
LH28F160S5-L/S5H-L
RY/BY# mode) will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO. After block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired.
5.7
Power Consumption
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solidstate storage can consume negligible power by lowering RP# to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP# is first raised to VIH. See Section 6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and Fig. 15, Fig. 16, Fig. 17 and Fig. 18 for more information.
5.6
Power-Up/Down Protection
The device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power supply (VPP or VCC) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = VIL regardless of its control inputs state.
- 34 -
LH28F160S5-L/S5H-L
6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings
Operating Temperature * LH28F160S5-L During Read, Erase, Write and Block Lock-Bit Configuration ... 0 to +70C (NOTE 1) Temperature under Bias ............. -10 to +80C * LH28F160S5H-L During Read, Erase, Write and Block Lock-Bit Configuration .... -40 to +85C (NOTE 2) Temperature under Bias............. -40 to +85C Storage Temperature ........................ -65 to +125C Voltage On Any Pin (except VCC, VPP) ..... -0.5 V to VCC+0.5 V (NOTE 3) VCC Supply Voltage ................. -0.2 to +7.0 V (NOTE 3) VPP Update Voltage during Erase, Write and Block Lock-Bit Configuration .... -0.2 to +7.0 V (NOTE 3) Output Short Circuit Current .............. 100 mA (NOTE 4)
NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. WARNING : Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES :
1. 2. 3. Operating temperature is for commercial product defined by this specification. Operating temperature is for extended temperature product defined by this specification. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5 V which, during transitions, may overshoot to VCC+2.0 V for periods < 20 ns. Output shorted for no more than one second. No more than one output shorted at a time.
4.
6.2
TA VCC1 VCC2
Operating Conditions
PARAMETER Operating Temperature VCC Supply Voltage (5.00.25 V) VCC Supply Voltage (5.00.5 V) NOTE 1 MIN. 0 -40 4.75 4.50 MAX. +70 +85 5.25 5.50 UNIT C C V V VERSIONS LH28F160S5-L LH28F160S5H-L LH28F160S5-L70/S5H-L70
SYMBOL
NOTE :
1. Test condition : Ambient temperature
6.2.1 CAPACITANCE (NOTE 1)
TA = +25C, f = 1 MHz SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance TYP. 7 9 MAX. 10 12 UNIT pF pF CONDITION VIN = 0.0 V VOUT = 0.0 V
NOTE :
1. Sampled, not 100% tested.
- 35 -
LH28F160S5-L/S5H-L 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
3.0 INPUT 0.0 1.5 TEST POINTS 1.5 OUTPUT
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 12 Transient Input/Output Reference Waveform for VCC = 5.00.25 V (High Speed Testing Configuration)
2.4 INPUT 0.45
2.0 TEST POINTS 0.8
2.0 OUTPUT 0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 13 Transient Input/Output Reference Waveform for VCC = 5.00.5 V (Standard Testing Configuration) Test Configuration Capacitance Loading Value
1.3 V 1N914
TEST CONFIGURATION VCC = 5.00.25 V (NOTE 1) VCC = 5.00.5 V
CL (pF) 30 100
NOTE :
1.
RL = 3.3 k DEVICE UNDER TEST CL CL Includes Jig Capacitance
Applied to high-speed products, LH28F160S5-L70 and LH28F160S5H-L70.
OUT
Fig. 14 Transient Equivalent Testing Load Circuit
- 36 -
LH28F160S5-L/S5H-L 6.2.3 DC CHARACTERISTICS
SYMBOL ILI ILO PARAMETER Input Load Current Output Leakage Current NOTE 1 1 VCC = 5.00.5 V TYP. MAX. 1 10 UNIT A A TEST CONDITIONS VCC = VCC Max. VIN = VCC or GND VCC = VCC Max. VOUT = VCC or GND CMOS Inputs VCC = VCC Max. CE# = RP# = VCC0.2 V TTL Inputs 2 VCC Deep PowerDown Current LH28F160S5-L LH28F160S5H-L 4 15 20 mA VCC = VCC Max. CE# = RP# = VIH RP# = GND0.2 V IOUT (STS) = 0 mA CMOS Inputs 50 ICCR VCC Read Current 1, 5, 6 65 mA mA VCC = VCC Max. CE# = GND f = 8 MHz, IOUT = 0 mA TTL Inputs VCC = VCC Max. CE# = VIL f = 8 MHz, IOUT = 0 mA ICCW VCC Write Current ((Multi) W/B Write or Set Block Lock-Bit) VCC Erase Current (Block Erase, Full Chip Erase, Clear Block Lock-Bits) 1, 7 35 mA VPP = 5.00.5 V
25 ICCS VCC Standby Current 1, 3, 6
100
A
ICCD
1
A
ICCE
1, 7
30
mA
VPP = 5.00.5 V
ICCWS VCC Write or Block Erase Suspend ICCES Current IPPS VPP Standby Current IPPR IPPD IPPW VPP Read Current VPP Deep Power-Down Current VPP Write Current ((Multi) W/B Write or Set Block Lock-Bit) VPP Erase Current (Block Erase, Full Chip Erase, Clear Block Lock-Bits) Current
1, 2 1 1 1 1, 7
1 2 10 0.1
10 15 200 5 80
mA A A A mA
CE# = VIH VPP VCC VPP > VCC RP# = GND0.2 V VPP = 5.00.5 V
IPPE
1, 7
40
mA
VPP = 5.00.5V
IPPWS VPP Write or Block Erase Suspend IPPES
1
10
200
A
VPP = VPPH1
- 37 -
LH28F160S5-L/S5H-L 6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL VIL VIH VOL VOH1 PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) VPP Lockout Voltage during Normal Operations VPP Voltage during Write or Erase Operations VCC Lockout Voltage NOTE 7 7 3, 7 3, 7 2.4 0.85 VOH2 3, 7 VCC VCC -0.4 VPPLK VPPH1 VLKO
1.
VCC = 5.00.5 V MIN. MAX. -0.5 2.0 0.8 VCC +0.5 0.45
UNIT V V V V V V
TEST CONDITIONS
VCC = VCC Min. IOL = 5.8 mA VCC = VCC Min. IOH = -2.5 mA VCC = VCC Min. IOH = -2.5 mA VCC = VCC Min. IOH = -100 A
4, 7 4.5 2.0
4.
1.5 5.5
V V V
NOTES :
All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25C. These currents are valid for all product versions (packages and speeds). ICCWS and ICCES are specified with the device deselected. If reading or (multi) word/byte writing in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. Includes STS. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.) and above VPPH1 (max.). Automatic Power Saving (APS) reduces typical ICCR to 1 mA at 5 V VCC in static operation. CMOS inputs are either VCC0.2 V or GND0.2 V. TTL inputs are either VIL or VIH. Sampled, not 100% tested.
2.
5. 6. 7.
3.
- 38 -
LH28F160S5-L/S5H-L 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE1) [LH28F160S5-L]
* VCC = 5.00.25 V, 5.00.5V, TA = 0 to +70C VCC0.25 V LH28F160S5-L70 VCC0.5 V SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFLQV tFHQV tFLQZ tELFL tELFH
1. 2. 3. 4.
(NOTE 5) (NOTE 5) (NOTE 4)
VERSIONS
UNIT MAX. 100 100 400 40 ns ns ns ns ns ns 35 ns ns 15 ns ns
LH28F160S5-L70 LH28F160S5-L10 MIN. 70 70 MAX. MIN. 80 80 80 400 35 0 25 0 10 0 0 0 10 0 30 0 0 70 400 30 0 MAX. MIN. 100
PARAMETER Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# to Output in High Z CE# Low to BYTE# High or Low
NOTE
2 2 3 3 3 3 3
3 3 3
70 25 5
80 30 5
100 30 5
ns ns ns
NOTES :
See AC Input/Output Reference Waveform (Fig. 12 and Fig. 13) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested. See Fig. 12 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. 5. See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
- 39 -
LH28F160S5-L/S5H-L 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) (NOTE1) [LH28F160S5H-L]
* VCC = 5.00.25 V, 5.00.5V, TA = -40 to +85C VCC0.25 V LH28F160S5H-L70 VCC0.5 V SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFLQV tFHQV tFLQZ tELFL tELFH
1. 2. 3. 4.
(NOTE 5) (NOTE 5) (NOTE 4)
VERSIONS
UNIT MAX. 100 100 400 40 ns ns ns ns ns ns 35 ns ns 15 ns ns
LH28F160S5H-L70 LH28F160S5H-L10 MIN. 70 70 MAX. MIN. 90 90 90 400 35 0 25 0 10 0 0 0 10 0 30 0 0 70 400 30 0 MAX. MIN. 100
PARAMETER Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# to Output in High Z CE# Low to BYTE# High or Low
NOTE
2 2 3 3 3 3 3
3 3 3
70 25 5
90 30 5
100 30 5
ns ns ns
NOTES :
See AC Input/Output Reference Waveform (Fig. 12 and Fig. 13) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested. See Fig. 12 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. 5. See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
- 40 -
LH28F160S5-L/S5H-L
VIH ADDRESSES (A) VIL VIH CE# (E) VIL VIH OE# (G) VIL VIH WE# (W) VIL VOH DATA (D/Q) VOL
Standby
Device Address Selection Address Stable
Data Valid
tAVAV
tEHQZ
tGHQZ
tGLQV tELQV tGLQX tELQX High Z tAVQV Valid Output tOH High Z
VCC tPHQV VIH RP# (P) VIL
NOTE :
CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Fig. 15 AC Waveform for Read Operations
- 41 -
LH28F160S5-L/S5H-L
VIH ADDRESSES (A) VIL VIH CE# (E) VIL VIH OE# (G) VIL VIH BYTE# (F) VIL VOH DATA (D/Q) (DQ0-DQ7) VOL VOH DATA (D/Q) (DQ8-DQ15) VOL
Standby
Device Address Selection Address Stable
Data Valid
tAVAV
tEHQZ tAVFL = tELFL
tELFL tFLQV = tAVQV tGLQV tELQV tGLQX tELQX High Z tAVQV tFLQZ High Z Data Output Data Output
tGHQZ
tOH Valid Output High Z
High Z
NOTE :
CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going high.
Fig. 16 BYTE# Timing Waveforms
- 42 -
LH28F160S5-L/S5H-L 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (NOTE 1) [LH28F160S5-L]
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to+70C VCC0.25 V LH28F160S5-L70 VCC0.5 V SYMBOL tAVAV tPHWL tELWL tWLWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVSL PARAMETER Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width WP# VIH Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to STS Going Low Write Recovery before Read VPP Hold from Valid SRD, STS High Z WP# VIH Hold from Valid SRD, STS High Z 2, 4 2, 4 2 2 3 3 NOTE MIN. 70 2 1 10 40 100 100 40 40 5 5 10 30 90 0 0 0 0 0 0 MAX.
(NOTE 6) (NOTE 6) (NOTE 5)
VERSIONS
LH28F160S5-L70 LH28F160S5-L10 MIN. 80 1 10 40 100 100 40 40 5 5 10 30 90 0 0 0 MAX. MIN. 100 1 10 40 100 100 40 40 5 5 10 30 90 MAX.
UNIT
ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES :
1. Read timing characteristics during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations are the same as during readonly operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. VPP should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 12 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
6.
2. 3.
4.
- 43 -
LH28F160S5-L/S5H-L 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.) (NOTE 1) [LH28F160S5H-L]
* VCC = 5.00.25 V, 5.00.5 V, TA = -40 to +85C VCC0.25 V LH28F160S5H-L70 VCC0.5 V SYMBOL tAVAV tPHWL tELWL tWLWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVSL PARAMETER Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width WP# VIH Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to STS Going Low Write Recovery before Read VPP Hold from Valid SRD, STS High Z WP# VIH Hold from Valid SRD, STS High Z 2, 4 2, 4 2 2 3 3 NOTE MIN. 70 2 1 10 40 100 100 40 40 5 5 10 30 90 0 0 0 0 0 0 MAX.
(NOTE 6) (NOTE 6) (NOTE 5)
VERSIONS
UNIT MAX. ns s ns ns ns ns ns ns ns ns ns ns 90 ns ns ns ns
LH28F160S5H-L70 LH28F160S5H-L10 MIN. 90 1 10 40 100 100 40 40 5 5 10 30 90 0 0 0 MAX. MIN. 100 1 10 40 100 100 40 40 5 5 10 30
NOTES :
1. Read timing characteristics during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations are the same as during readonly operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. VPP should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 12 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
6.
2. 3.
4.
- 44 -
LH28F160S5-L/S5H-L
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH ADDRESSES (A) VIL VIH CE# (E) VIL VIH OE# (G) VIL tWHWL VIH WE# (W) VIL VIH DATA (D/Q) VIL High Z STS (R) VOL VIH WP# (S) VIL VIH RP# (P) VIL tVPWH VPPH1 VPP (V) VPPLK VIL tQVVL tSHWH tQVSL High Z tPHWL tWHRL tWLWH tDVWH tWHDX DIN DIN Valid SRD DIN tWHQV1/2/3/4 tELWL tWHEH tWHGL AIN tAVAV AIN tAVWH tWHAX
NOTES :
1. 2. 3. 4. 5. 6. 7. VCC power-up and standby. Write erase or write setup. Write erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Fig. 17 AC Waveform for WE#-Controlled Write Operations
- 45 -
LH28F160S5-L/S5H-L 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES [LH28F160S5-L]
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C VCC0.25 V LH28F160S5-L70 VCC0.5 V SYMBOL tAVAV tPHEL tWLEL tELEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVSL PARAMETER Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width WP# VIH Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to STS Going Low Write Recovery before Read VPP Hold from Valid SRD, STS High Z WP# VIH Hold from Valid SRD, STS High Z 2, 4 2, 4 2 2 3 3 2 NOTE MIN. 70 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 0 0 0 MAX.
(NOTE 6) (NOTE 6) (NOTE 5)
(NOTE 1)
VERSIONS
LH28F160S5-L70 LH28F160S5-L10 MIN. 80 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 MAX. MIN. 100 1 0 50 100 100 40 40 5 5 0 25 90 MAX.
UNIT
ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES :
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. VPP should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 12 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
2. 3.
6.
4.
- 46 -
LH28F160S5-L/S5H-L 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) [LH28F160S5H-L]
* VCC = 5.00.25 V, 5.00.5 V, TA = -40 to +85C VCC0.25 V LH28F160S5H-L70 VCC0.5 V SYMBOL tAVAV tPHEL tWLEL tELEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVSL PARAMETER Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width WP# VIH Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to STS Going Low Write Recovery before Read VPP Hold from Valid SRD, STS High Z WP# VIH Hold from Valid SRD, STS High Z 2, 4 2, 4 2 2 3 3 2 NOTE MIN. 70 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 0 0 0 MAX.
(NOTE 6) (NOTE 6) (NOTE 5)
(NOTE 1)
VERSIONS
LH28F160S5H-L70 LH28F160S5H-L10 MIN. 90 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 MAX. MIN. 100 1 0 50 100 100 40 40 5 5 0 25 90 MAX.
UNIT
ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES :
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. VPP should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 12 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. See Fig. 13 "Transient Input/Output Reference Waveform" and Fig. 14 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
2. 3.
6.
4.
- 47 -
LH28F160S5-L/S5H-L
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH ADDRESSES (A) VIL VIH WE# (W) VIL VIH OE# (G) VIL tEHEL VIH CE# (E) VIL VIH DATA (D/Q) VIL High Z STS (R) VIL VIH WP# (S) VIL VIH RP# (P) VIL tVPEH VPPH1 VPP (V) VPPLK VIL tQVVL tSHEH tQVSL High Z tPHEL tEHRL tELEH tDVEH tEHDX DIN DIN Valid SRD DIN tEHQV1/2/3/4 tWLEL tEHWH tEHGL AIN tAVAV AIN tAVEH tEHAX
NOTES :
1. 2. 3. 4. 5. 6. 7. VCC power-up and standby. Write erase or write setup. Write erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Fig. 18 AC Waveform for CE#-Controlled Write Operations
- 48 -
LH28F160S5-L/S5H-L 6.2.7 RESET OPERATIONS
High Z STS (R) VOL VIH RP# (P) VIL tPLPH (A) Reset During Read Array Mode High Z STS (R) VOL RP# (P) VIH VIL tPLPH (B) Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write or Block Lock-Bit Configuration 5V VCC VIL VIH RP# (P) VIL (C) VCC Power Up Timing t5VPH tPLRH
Fig. 19 AC Waveform for Reset Operation Reset AC Specifications SYMBOL tPLPH tPLRH t5VPH PARAMETER RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during Block Erase, Full Chip Erase, (Multi) Word/Byte Write or Block Lock-Bit Configuration VCC 4.5 V to RP# High
3. 4.
(NOTE 1)
NOTE
VCC = 5.00.5 V MIN. MAX. 100
UNIT ns
2, 3 4 100
13.1
s ns
NOTES :
1. 2. These specifications are valid for all product versions (packages and speeds). If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is not executing, the reset will complete within 100 ns. A reset time, tPHQV, is required from the latter of STS going High Z or RP# going high until outputs are valid. When the device power-up, holding RP#-low minimum 100 ns is required after VCC has been in predefined range and also has been in stable there.
- 49 -
LH28F160S5-L/S5H-L 6.2.8 BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4)
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C or -40 to +85C SYMBOL PARAMETER NOTE 2 2 2 2 2 2 2 MIN. VCC = 5.00.5 V TYP. (NOTE 1) MAX. 9.24 9.24 2 0.31 0.61 0.13 0.34 10.9 2 2 9.24 0.34 5.6 9.4 TBD TBD TBD 3.7 7.5 1.5 10 TBD TBD TBD 7 13.1 UNIT s s s s s s s s s s s s
tWHQV1 Word/Byte Write Time (using W/B write, in word mode) tEHQV1 tWHQV1 tEHQV1 Word/Byte Write Time (using W/B write, in byte mode) Word/Byte Write Time (using multi word/byte write) Block Write Time (using W/B write, in word mode) Block Write Time (using W/B write, in byte mode) Block Write Time (using multi word/byte write) tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHRH1 tEHRH1 tWHRH2 tEHRH2 Block Erase Time Full Chip Erase Time Set Block Lock-Bit Time Clear Block Lock-Bits Time Write Suspend Latency Time to Read Erase Suspend Latency Time to Read
NOTES :
1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding block lock-bits are not set. Subject to change based on device characterization. Excludes system-level overhead. 3. 4. These performance numbers are valid for all speed versions. Sampled, not 100% tested.
2.
- 50 -
LH28F160S5-L/S5H-L
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products L H 2 8 F 1 6 0 S 5 (H) T - L 7 0 Device Density 160 = 16 M-bit Architecture S = Symmetrical Block Power Supply Type 5 = Smart 5 Technology Operating Temperature Blank = 0 to +70C H = - 40 to +85C Access Speed (ns) 70 : 70 ns (5.00.25 V), 80 ns (5.00.5 V) [LH28F160S5-L]/ 90 ns (5.00.5 V) [LH28F160S5H-L] 10 : 100 ns (5.00.5 V) Package T = 56-pin TSOP (I) (TSOP056-P-1420) Normal bend R = 56-pin TSOP (I) (TSOP056-P-1420) Reverse bend NS = 56-pin SSOP (SSOP056-P-0600)5 [LH28F160S5-L] B = 64-ball CSP (FBGA064-P-0811) D = 64-pin SDIP (SDIP064-P-0750)5
5 Under development
VALID OPERATIONAL COMBINATIONS VCC = 5.00.5 V VCC = 5.00.25 V OPTION 1 2 3 ORDER CODE LH28F160S5X-L70 LH28F160S5HX-L70 LH28F160S5XX-L10 100 pF load, TTL I/O Levels 80 ns 90 ns 100 ns 30 pF load, 1.5 V I/O Levels 70 ns 70 ns
- 51 -
0.125 0.05 0.08 M
1
56 TSOP (TSOP056-P-1420)
28
0.125 0.435 0.115 0.1 0.995 0.1 1.2MAX.
20.0 0.3 18.40.2
19.0 0.3 29 Package base plane
56
0.5TYP.
56 _ 0.2 0.08
14.0 0.2
0.10
PACKAGING
PACKAGING
56 SSOP (SSOP056-P-0600)
_ 56 0.30.1 56
_ P 0.8TYP.
0.15 29
M
16.00.3
13.30.2
1
0.15
(1.28)
23.70.2
28
1.85MAX.
0.150.05
Package base plane 0.10 0.520.1
(14.4)
PACKAGING
64 CSP (FBGA064-P-0811)
A B
/ / 0.1 S S 11.000.2
+
0.4TYP.
1.2MAX.
8.00
+ 0.2
Land hole diameter
for ball mounting
0.1 S
H D
A 1 0.450.03 8
0.30 0.15
M M
S S
AB CD
0.4TYP. 0.8TYP. 1.2TYP.
2.7TYP. 0.8TYP. 0.4TYP.
C
0.350.05
PACKAGING
Package Outline
64 SDIP (SDIP064-P-0750)
(Unit : mm)
64
33
SDIP : SOP : SSOP: TSOP : CSP :
17.0 0.25
Shrink DIP Small Outline Package Shrink SOP Thin SOP Chip Size Package (FBGA)
DIP : Dual In-line Package
4.250.35 5.20.5
1
58.0 0.3
32
19.05 TYP.
0.51 MIN.
3.250.3
1.778 TYP.
0.46 0.1
0.25
M
0.25 0
0 .05
15
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Fax: (360) 834-8903 http://www.sharpsma.com
SHARP Microelectronics Europe Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Fax: (49) 40 2376-2232 http://www.sharpsme.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Fax: +81-743-65-1532 http://www.sharp.co.jp

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